Starting with VMLAB version 3.15, it's possible to create external user components that emulate AVR peripherals such as timers, UARTs, etc. The components on this page currently implement only a few of the peripherals found in the ATmega168. My long term goal is to create a user component for every peripheral found in all of the ATmega and ATtiny series of microcontrollers. These components are licensed under the
GNU LGPL v2.1.
The EEPROM component makes use of the ShineInHex control which was developed by
The MASM Forum member "ramguru". The original binaries, source code, and documentation for the control can be found in
this thread on the same forum.
Usage
To simulate a ATmega168 microcontroller with the new peripheral components, use the following directive in your project file:
.MICRO "ATmega168b"The "b" at the end of the micro name is necessary to select the new model; without it, the old internal ATmega168 model would be used. Note that the default fuses on a brand new ATmega168 chip are CKSEL=0010 and CKDIV8=0, and these select the internal 8Mhz oscillator with a divide by 8 prescaler. This is also the default in the "ATmega168b" model, which will
ignore any
.CLOCK directive in the project unless the user explicitly overrides the default fuse settings. For example, to specify an external 11.059Mhz clock source, the project file should contain the following:
.MICRO "ATmega168b" "CKSEL=0000 CKDIV8=1"
.CLOCK 11.059MegFinally, please keep in mind that apart from the peripherals listed here, all other peripherals are still implemented using the old builtin models that don't quite match the real hardware of the 168.
Downloads
When downloading a new version of the AVR peripherals, always make sure to replace every one of the old DLL and INI files in VMLAB's "mculib" directory with the newer versions from the zip file's "mculib" directory. Because these components closely interact with each other, updating only some of the files could cause unpredictable behavior and even crashes due to the version mismatch. Also note that starting with v0.6, the zip file now contains a "ShineInHex.dll" file which should be added to VMLAB's "bin" directory.
Linux/Wine Users: When installing the useravr zip files from this website, make sure that you end up with only one INI file in the "mculib" directory. VMLAB 3.15 comes with an "ATmega168b.ini" file, but in my own zip files, I inadvertently changed the capitalization to "AtMega168b.ini". Because Linux files are case-sensitive, it's possible to end up with
two files that differ only in the capitalization, and VMLAB may open the wrong one. Starting with version 0.6.1, the filename capitalization is back to the original "ATmega168b.ini".
Supported Peripherals
This section explains in great detail what AVR peripherals are currently emulated and how accurate that emulation is. Text in
blue is used to describe any unusual behavior that may be confusing for someone who is new
to VMLAB or AVRs. Text in
red describes any differences between the behavior of the emulated peripheral and the real AVR hardware.
In general, 1 to 6 clock cycle delays due to synchronization, edge detection circuits, etc. will not be emulated.
- General I/O Pins
- PORTx, PINx, DDRx registers are emulated. Pin toggling is supported. Writing a 1 bit to a PINx bit will toggle the corresponding bit in the PORTx register.
- If another peripheral overrides the direction and/or output value of a pin, then that pin will not automatically return to its previous state (as defined in DDRx and PORTx) when the peripheral function is turned off. The pin state will not change until the DDRx and/or PORTx registers are updated again.
- The 1.5 clock cycle input delay due to synchronization of the I/O pin is not emulated. After writing PORTx, VMLAB doesn't require a "nop" instruction when immediately reading back the software assigned pin value through PINx. See the "Reading the Pin Value" section in the datasheet for more information.
- Sleep Mode
- The SMCR register and the SLEEP instruction are emulated. All sleep modes are supported.
- Only the WDOG, TIMER0, TIMER1, TIMER2, COMP, and EEPROM peripherals are currently guaranteed to behave correctly during sleep mode.
- Watchdog
- All watchdog timer modes are emulated including the Interrupt Mode, System Reset Mode, and Interrupt and System Reset Mode.
- The WDTON fuse is supported; if programmed (WDTON=0) the watchdog is forced into System Reset Mode.
- When modifying the WDTCSR register in the GUI, keep in mind that changing some bits in this register requires a timed update sequence. You may have to breakpoint the simulation first to keep the WDCE bit from being automatically cleared while modifying the register.
- The emulated watchdog timer always runs at 128kHz. The watchdog timer frequency in a real AVR is somewhat dependent on both operating temperature and supply voltage.
- TIMER0
- All timer registers are emulated.
The PRTIM0 bit in PRR is emulated. All waveform
generation modes, output compare modes, and timer clock sources are
emulated.
- The
OCR0A/B registers are double-buffered in PWM waveform generation modes. Changing either register in the
GUI will actually change the value in the buffer first. You may have to right click on the registers and select
"Modify / browse" from the pop-up menu to make your changes atomic.
- TIMER1
- All timer registers are emulated.
The PRTIM1 bit in PRR is emulated. All waveform
generation modes, output compare modes, input capture, and timer clock sources are
emulated.
- The
OCR0A/B regis double-buffered in PWM waveform generation modes. Changing either register in the
GUI will actually change the value in the buffer first. You may have to right click on the registers and select
"Modify / browse" from the pop-up menu to make your changes atomic.
- The input capture noise canceler is not emulated. Setting the ICNC1 bit in TCCR1B has no effect, and VMLAB neither filters nor delays the input capture source by 4 system clock cycles.
- TIMER2
- All timer registers are emulated. The PRTIM2 bit in PRR is emulated. All waveform generation modes, output compare modes, and timer clock sources are emulated.
- Asynchronous operation with either a 32.768kHz watch crystal or an external clock signal on the TOSC1 pin is emulated. All side-effects described in the "Asynchronous Operation of Timer/Counter2" section in the datasheet are emulated, and VMLAB will issue warnings if any potentially undesirable behavior occurs.
- The datasheet warns that all timer registers except for ASSR may be corrupted when switching to and from asynchronous mode or when waking up from sleep while in asynchronous mode. VMLAB can optionally emulate this behavior by setting all affected registers to unknown (i.e. XXXXXXXX) if the "Async Corrupt" option in the GUI is checked.
- In asynchronous mode, updates to all registers except ASSR are delayed by two asynchronous clock cycles. When modifying the registers in the GUI, the new values will not be immediately visible. This is in addition to the OCR2A/B double-buffering done in PWM waveform generation mode. You may have to right click on the registers and select
"Modify / browse" from the pop-up menu to make your changes atomic.
- Asynchronous mode can be enabled while using an external system clock (based on CKSEL fuse settings). On real hardware, asynchronous mode can only be used with the internal RC oscillator system clock because the TOSC and XTAL functions are shared by the same set of pins.
- Signal changes on the TOSC1/2 pins continue to trigger PCINTx interrupts while the timer is in asynchronous mode.
- The datasheet advises waiting at least 1 second after enabling asynchronous operation so the oscillator can stabilize. VMLAB does not enforce nor emulate this behavior; the timer is immediately available for use after entering asynchronous mode.
- Timer Prescalers
- The free running timer prescalers are emulated. Timers sharing the same prescaler module and using the same clock divisor will increment in unison.
- The GTCCR register is emulated; timer synchronization mode and synchronous/asynchronous prescaler reset are supported.
- Analog Comparator
- All bits in the ACSR register and DIDR1 are supported. The Analog Comparator Input Capture is supported for TIMER1.
- At this time, the analog comparator multiplexed input is not supported. This will become possible once the A/D Converter is implemented with a separate DLL.
- EEPROM
- All bits in the EECR are emulated, and all programming modes
defined by EEPM are supported. The level triggered ERDY interrupt is emulated.
- The component will not simulate any EEPROM programming delay to
speed up the simulation (the EEPE bit in EECR always reads 0), unless
the "Simulate erase/write time" option in the GUI is checked.
- The "Save" and "Load" buttons in the GUI can be used to transfer the EEPROM memory contents to and from a file at any time. Supported file formats include Intel HEX, Motorola S-Record, Atmel Generic, and raw binary data. The "Erase" button can also be used to reset the EEPROM to a fully erased $FF state.
- The "View" button will open a separate hex editor window to allow manual editing of the EEPROM memory contents. Right clicking in the editor window opens a context menu with commands to copy the current data selection to the Windows clipboard in several formats and to display a "Find" dialog box, allowing searches for UTF-8/16 string patterns and for hex data in either little or big endian layout. The editor also supports a multi-level Undo/Redo (currently only accessible from the context menu and not via Ctrl+Z or Ctrl+Y) and has support for selection filling (typing hex or ASCII characters while a selection is active will change all the bytes included in that selection).
- Due to a bug in the current VMLAB version, none of the GUI buttons in the control will respond to mouse clicks until the project file is built at least once (using the Project->Build menu item or the F9 shortcut key). Afterwards, the buttons will continue to work normally until a new project file is opened.
- In the next VMLAB version, the "Persistent" checkbox will be enabled and the EEPROM memory contents will be automatically preserved across multiple simulation runs.
- On real AVR hardware, the Flash and EEPROM memories cannot be programmed at the same time. Currently VMLAB neither detects nor enforces this restriction.
Version History
- v0.6.1 - 2011-02-04 - Workarounds for timer interrupt issues with flag and mask bits
- v0.6 - 2010-07-01 - EEPROM model released
- v0.5.1 - 2010-03-24 - Fixed COMP interrupt problem
- v0.5 - 2010-03-22 - COMP model released
- v0.4 - 2010-02-26 - WDOG model released
- v0.3 - 2010-01-03 - TIMER1 model released
- v0.2 - 2009-10-09 - TIMER2 model released
- v0.1 - 2009-09-15 - TIMER0 model released
Screenshots
The screenshots below show off the GUI interface for all the AVR peripherals described on this page:
