ThVortex

Break On Edge

This component is intended as a debugging and testing aid, as it will breakpoint the simulation on every rising edge of the <TRIGGER> pin. By combining this component with others, such as the Digital Signal Delay or the builtin NAND gate ("ND2"), complex breakpoint conditions may be defined without having to write a new application specific user component.

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Usage

; To use this component, use the following component definition:
;
; X _break(<Delay>) <TRIGGER> <CANCEL>
;
; A breakpoint will occur on every rising edge of the <TRIGGER> pin. If the
; <Delay> argument is zero, then the breakpoint occurs immediately during the
; same time step as the rising edge. If the <Delay> argument is non zero, then
; a rising <TRIGGER> edge schedules a future breakpoint to occur <Delay>
; seconds after the rising edge was detected. Once a future breakpoint is
; scheduled in this manner, any further rising edges on <TRIGGER> are ignored
; and will not schedule additional breakpoints, until the original breakpoint
; is hit. Once the simulation is resumed, the <TRIGGER> pin will once again be
; monitored for rising edges.
;
; For normal operation as described above, the <CANCEL> pin must remain low.
; However, if the <CANCEL> pin becomes high, then any pending breakpoints (in
; case <Delay> is non zero) are cancelled. In addition, as long as <CANCEL>
; remains high, any further rising edges on <TRIGGER> will be ignored until the
; <CANCEL> pin goes low again.

Example

X _break(10u) PB0 GND

Potential Uses:

  1. Since a NAND gate can implement all other logic gates, one can breakpoint on an arbitrary logic function by building the appropriate trigger circuit using VMLAB's builtin "ND2" component. The example below breaks on the rising edge of: "/A * B + C" (the / denotes a NOT gate, the * an AND, and the + an OR). Note that the node names in this example are based on the Reverse Polish Notation to indicate which part of the logic function they represent:

    X ND2 A VDD An        ; An = /A
    X ND2 An B AnBan      ; AnBan = /( /A * B )
    X ND2 C VDD Cn        ; Cn = /C
    X ND2 AnBan Cn FUNC   ; FUNC = /( /( /A * B ) * /C )
    X _break(0) FUNC GND  ; FUNC = /A * B + C (Demorgan's Theorem)

  2. Using a non-zero <Delay> argument and tying the <TRIGGER> pin to VDD, makes it possible to set breakpoints that always occur at a fixed time in the simulation:

    X _break(100m) VDD GND  ; Break at absolute 100ms of the simulated time

  3. A "break" component with a delay can be used to breakpoint the simulation each time a byte is transmitted via a UART interface. For example, if the transmission runs at 9600bps and uses 8N1 data format, then it takes approximately 1ms to transmit a single character:

    X ND2 TX VDD TXn        ; Invert TX to break on falling start bit edge
    X _break(1m) TXn GND    ; Trigger on start bit; wait for char
  4. Continuing the UART example from above and adding a "delay" (Digital Signal Delay) component, it now becomes possible to break on the first byte transmitted after the UART has remained idle for some user specified time (100 milliseconds in this example):

    X _delay(100m 50u) TX IDLE  ; IDLE high only if TX remains high for 100ms
    X ND2 TX VDD TXn            ; Invert TX to break on falling start bit edge
    X ND2 TXn IDLE FUNCn        ; FUNCn = /( /TX * IDLE )
    X ND2 FUNCn VDD FUNC        ; FUNC = /TX * IDLE
    X _break(1m) FUNC GND       ; Break on start bit after idle; wait for char

  5. Finally, by combining a pair of "delay" and "break" components and using the <CANCEL> pin, it becomes possible to automatically verify timing constraints on a signal. For example, let's assume that PWM is a Pulse Width Modulated signal whose logic 1 pulse must be at least 4ms long but not more than 6ms. This constraint can be enforced as follows:

    ; MAXLENGTH is high when a high pulse on PWM is longer than 6ms, and
    ; the simulation stops on a breakpoint via the TOOLONG instance.
    XTSTLONG _delay(6m 0) PWM MAXLENGTH
    XTOOLONG _break(0) MAXLENGTH GND

    ; MINLENGTH signal is high if a high pulse on PWM is at least 4ms long.
    ; If the high pulse is long enough, then MINLENGTH cancels the pending
    ; TOOSHORT breakpoint.
    XTSTSHORT _delay(4m 0) PWM MINLENGTH
    XTOOSHORT _break(6m) PWM MINLENGTH